Senior Engineer (Level 1)- FPGA Design

Position: Senior Engineer (Level 1)- FPGA Design Job Description: Principal Accountabilities * Familiar with FPGA/ASIC design cycle Design, Development, Simulation, Test & Debug, Verification & Validation for Embedded Data acquisitions applications *Perform FPGA/ASIC coding Development in languages like Verilog, VHDL, System Verilog Job Complexity Job complexity may vary among jobs within this job level and will align with one of the job complexities listed below: (1) Incumbent has knowledge an…

This job is sourced from our partner network. You are applying through the Job Direction portal.