Senior Engineer (Level 2)

Position: Senior Engineer (Level 2) Job Description: Principal Accountabilities * Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis etc in ASIC PNR Flow *Execute the block level place and route assignments from Netlist through GDS flow * Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed. * Close STA timing acr…

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