Senior Engineer (Level 1)

Position: Senior Engineer (Level 1) Job Description: Principal Accountabilities * Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM. * Execute block level place and route assignments from Netlist through GDS flow. * Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed. * Close STA timing across all corners and modes fo…

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